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mos integrated circuit m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 16-bit single-chip microcontrollers document no. u14125ej1v0ds00 (1st edition) date published november 2000 n cp(k) printed in japan data sheet description the m pd78f4216a/78f4218a and 78f4216ay/78f4218ay are products of m pd784216a/784218a, 784216ay/784218ay subseries in the 78k/iv series. the m pd78f4216a/78f4218a have flash memory in place of the internal rom of the m pd784216a/784218a. the incorporation of flash memory allows a program to be written or erased while mounted on the target board. the m pd78f4216ay/78f4218ay are based on the m pd78f4216a/78f4218a subseries with the addition of a multimaster-supporting i 2 c bus interface. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. m m m m pd784216a, 784216ay subseries users manual hardware: u13570e m m m m pd784218a, 784218ay subseries users manual hardware: u12970e 78k/iv series users manual instructions: u10905e features pin compatible with the mask rom products flash memory: 128 kb ( m pd78f4216a/78f4216ay) 256 kb ( m pd78f4218a/78f4218ay) internal ram: 8,192 bytes ( m pd78f4216a/78f4216ay) 12,800 bytes ( m pd78f4218a/78f4218ay) supply voltage: v dd = 1.9 to 5.5 v applications cellular phones, phs, cordless telephones, cd-rom, av equipment unless otherwise specified, references in this document to the m m m m pd78f4218ay refer to the m m m m pd78f4216a, 78f4218a, 78f4216ay, and 78f4218ay. 2000 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
data sheet u14125ej1v0ds00 2 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay ordering information part number package internal rom (bytes) internal ram (bytes) m pd78f4216agc-8eu 100-pin plastic lqfp (fine pitch) (14 14) 128 k 8,192 m pd78f4216agf-3ba 100-pin plastic qfp (14 20) 128 k 8,192 m pd78f4218agc-8eu 100-pin plastic lqfp (fine pitch) (14 14) 256 k 12,800 m pd78f4218agf-3ba 100-pin plastic qfp (14 20) 256 k 12,800 m pd78f4216aygc-8eu 100-pin plastic lqfp (fine pitch) (14 14) 128 k 8,192 m pd78f4216aygf-3ba 100-pin plastic qfp (14 20) 128 k 8,192 m pd78f4218aygc-8eu 100-pin plastic lqfp (fine pitch) (14 14) 256 k 12,800 m pd78f4218aygf-3ba 100-pin plastic qfp (14 20) 256 k 12,800
data sheet u14125ej1v0ds00 3 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 78k/iv series lineup pd784026 pd784956a pd784908 pd784915 pd784928 pd784928y pd784046 pd784054 pd784216a pd784216ay pd784038 pd784038y pd784225y pd784225 pd784218ay pd784218a enhanced a/d converter, 16-bit timer, and power management enhanced internal memory capacity pin-compatible with the pd784026 supports i 2 c bus supports multimaster i 2 c bus 80-pin, rom correction added supports multimaster i 2 c bus enhanced internal memory capacity, rom correction added 100-pin, enhanced i/o and internal memory capacity on-chip 10-bit a/d converter for dc inverter control on-chip iebus tm controller software servo control on-chip analog circuit for vcrs enhanced timer supports multimaster i 2 c bus enhanced functions of the pd784915 standard models assp models supports multimaster i 2 c bus : products in mass-production : products under development m m pd784976 on-chip vfd controller/driver m m m m m m m m m m m m m m m m m pd784938a enhanced functions of the pd784908, enhanced internal memory capacity, rom correction added. m m pd784967 m enhanced functions of the pd784938a, enhanced i/o and internal memory capacity. m
data sheet u14125ej1v0ds00 4 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay overview of functions (1/2) part number item m pd78f4216a, m pd78f4216ay m pd78f4218a, m pd78f4218ay number of basic instructions (mnemonics) 113 general-purpose registers 8 bits 16 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution time 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (@f xx = 12.5 mhz operation with main system clock) 61 m s (@f xt = 32.768 khz operation with sub system clock) flash memory 128 kb 256 kb internal memory ram 8,192 bytes 12,800 bytes memory space 1 mb with program and data spaces combined total 86 cmos input 8 cmos i/o 72 i/o ports n-ch open-drain i/o 6 pins with pull-up resistor 70 led direct drive output 22 pins with additional functions note 1 middle-voltage pin 6 real-time output port 4 bits 2 or 8 bits 1 timer/event counter: timer counter 1 pulse output (16-bit) capture/compare register 2 ppg output square wave output one-shot pulse output timer/event counter 1: timer counter 1 pulse output (8-bit) compare register 1 pwm output square wave output timer/event counter 2: timer counter 1 pulse output (8-bit) compare register 1 pwm output square wave output timer/event counter 5: timer counter 1 pulse output (8-bit) compare register 1 pwm output square wave output timer/event counter 6: timer counter 1 pulse output (8-bit) compare register 1 pwm output square wave output timer/event counter 7: timer counter 1 pulse output (8-bit) compare register 1 pwm output square wave output timer/event counter timer/event counter 8: timer counter 1 pulse output (8-bit) compare register 1 pwm output square wave output serial interface uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) csi (3-wire serial i/o, multimaster supporting i 2 c bus note 2 ): 1 channel a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels notes 1. pins with additional functions are included with the i/o pins. 2. m pd78f4216ay, 78f4218ay only
data sheet u14125ej1v0ds00 5 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay overview of functions (2/2) part number item m pd78f4216a, m pd78f4216ay m pd78f4218a, m pd78f4218ay clock output selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt buzzer output selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 watch timer 1 channel watchdog timer 1 channel standby halt/stop/idle modes in low power consumption mode (with sub system clock): halt/idle m odes hardware sources 29 (internal: 20, external: 9) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 interrupt maskable internal: 19, external: 8 4 programmable priority levels 3 service modes: vectored interrupt/macro service/context switching supply voltage v dd = 1.9 to 5.5 v package 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20)
data sheet u14125ej1v0ds00 6 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay contents 1. differences among models in m m m m pd784216a/784216ay, 784218a/784218ay subseries ...................................................................................................................... ....................... 7 2. pin configuration (top view) ............................................................................................. ...... 8 3. block diagram ............................................................................................................ ................... 11 4. pin functions ............................................................................................................ ...................... 12 4.1 port pins ................................................................................................................ ..................... 12 4.2 non-port pins ............................................................................................................ ................. 14 4.3 pin i/o circuits and recommended connections of unused pins ....................................... 16 5. internal memory size switching register (ims) ................................................................ 20 6. programming flash memory.................................................................................................. ... 22 6.1 selecting communication mode ............................................................................................. .22 6.2 flash memory programming function .................................................................................... 23 6.3 connecting flashpro ll and flashpro lll ................................................................................... 2 4 7. electrical specifications ................................................................................................ ........ 25 8. package drawings ......................................................................................................... .............. 47 9. recommended soldering conditions .................................................................................. 49 appendix a. development tools .............................................................................................. .. 50 appendix b. related documents .............................................................................................. .. 53
data sheet u14125ej1v0ds00 7 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 1. differences among models in m m m m pd784216a/784216ay, 784218a/784218ay subseries the only difference among the m pd784214a, 784215a, 784216a, 784217a, and 784218a lies in the internal memory capacity. the m pd784214ay, 784215ay, 784216ay, 784217ay, and 784218ay are models with the addition of an i 2 c bus control function. the m pd78f4216a, 78f4216ay, 78f4218a, and 78f4218ay are provided with a 128 kb/256 kb flash memory instead of the mask rom of the above models. these differences are summarized in table 1-1. table 1-1. differences among models in m m m m pd784216a/784216ay, 784218a/784218ay subseries part number item m pd784214a, m pd784214ay m pd784215a, m pd784215ay m pd784216a, m pd784216ay m pd784217a, m pd784217ay m pd784218a, m pd784218ay m pd78f4216a, m pd78f4216ay m pd78f4218a, m pd78f4218ay internal rom 96 kb (mask rom) 128 kb (mask rom) 192 kb (mask rom) 256 kb (mask rom) 128 kb (flash memory) 256 kb (flash memory) internal ram 3,584 bytes 5,120 bytes 8,192 bytes 12,800 bytes 8,192 bytes 12,800 bytes internal memory size switching register (ims) not provided provided note rom correction not provided provided not provided provided external access status function not provided provided not provided provided supply voltage v dd = 1.8 to 5.5 v v dd = 1.9 to 5.5 v electrical specifications recommended soldering conditions refer to the data sheet for each device. exa pin not provided provided not provided provided test pin provided not provided v pp pin not provided provided note the internal flash memory capacity and internal ram capacity can be changed using the internal memory size switching register (ims). caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask rom version.
data sheet u14125ej1v0ds00 8 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 2. pin configuration (top view) 100-pin plastic lqfp (fine pitch) (14 14) m m m m pd78f4216agc-8eu, m m m m pd78f4218agc-8eu, m m m m pd78f4216aygc-8eu, m m m m pd78f4218aygc-8eu notes 1. connect the v pp pin to v ss directly or via a pull-down resistor in normal operation mode. connect the v pp pin to v ss via a pull-down resistor in a system in which the on-chip flash memory is written while mounted on the target board. for the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 w to 10 k w . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . 4. the scl0 and sda0 pins are available in the m pd78f4216ay, 78f4218ay only. 5. the exa pin is available in the m pd78f4218a, 78f4218ay only. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 76 p120/rtp0 p121/rtp1 p122/rtp2 p123/rtp3 p124/rtp4 p125/rtp5 p126/rtp6 p127/rtp7 v dd x2 x1 v ss xt2 xt1 reset p00/intp0 p01/intp1 p02/intp2/nmi p03/intp3 p04/intp4 p05/intp5 p06/intp6 av dd note 2 av ref0 p10/ani0 p62/a18 p61/a17 p60/a16 v ss p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p87/a7 p86/a6 p85/a5 p84/a4 p83/a3 p95 p94 p93 p92 p91 p90 v pp note 1 p37/exa note 5 p36/ti01 p35/ti00 p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p103/ti8/to8 p102/ti7/to7 p101/ti6/to6 p100/ti5/to5 v dd p67/astb p66/wait p65/wr p64/rd p63/a19 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss note 3 p130/ano0 p131/ano1 av ref1 p70/rxd2/si2 p71/txd2/so2 p72/asck2/sck2 p20/rxd1/si1 p21/txd1/so1 p22/asck1/sck1 p23/pcl p24/buz p25/si0/sda0 note 4 p26/so0 p27/sck0/scl0 note 4 p80/a0 p81/a1 p82/a2 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 26 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
data sheet u14125ej1v0ds00 9 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 100-pin plastic qfp (14 20) m m m m pd78f4216agf-3ba, m m m m pd78f4218agf-3ba, m m m m pd78f4216aygf-3ba, m m m m pd78f4218aygf-3ba notes 1. connect the v pp pin to v ss directly or via a pull-down resistor in normal operation mode. connect the v pp pin to v ss via a pull-down resistor in a system in which the on-chip flash memory is written while mounted on the target board. for the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 w to 10 k w . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . 4. the scl0 and sda0 pins are available in the m pd78f4216ay, 78f4218ay only. 5. the exa pin is available in the m pd78f4218a, 78f4218ay only. 100 v ss p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p87/a7 p86/a6 p85/a5 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p84/a4 p83/a3 p82/a2 p81/a1 p80/a0 p27/sck0/scl0 note 4 p26/so0 p25/si0/sda0 note 4 p24/buz p23/pcl p22/asck1/sck1 p21/txd1/so1 p20/rxd1/si1 p72/asck2/sck2 p71/txd2/so2 p70/rxd2/si2 av ref1 p131/ano1 p130/ano0 av ss note 3 p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd note 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p60/a16 p61/a17 p62/a18 p63/a19 p64/rd p65/wr p66/wait p67/astb v dd p100/ti5/to5 p101/ti6/to6 p102/ti7/to7 p103/ti8/to8 p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/ti00 p36/ti01 p37/exa note 5 v pp note 1 p90 p91 p92 p93 p94 p95 p120/rtp0 p121/rtp1 p122/rtp2 p123/rtp3 p124/rtp4 p125/rtp5 p126/rtp6 p127/rtp7 v dd x2 x1 v ss xt2 xt1 reset p00/intp0 p01/intp1 p02/intp2/nmi p03/intp3 p04/intp4 p05/intp5 p06/intp6 31 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
data sheet u14125ej1v0ds00 10 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay a0 to a19: address bus p120 to p127: port 12 ad0 to ad7: address/data bus p130, p131: port 13 ani0 to ani7: analog input pcl: programmable clock ano0, ano1: analog output rd: read strobe asck1, asck2: asynchronous serial clock reset: reset astb: address strobe rtp0 to rtp7: real-time output port av dd : analog power supply rxd1, rxd2: receive data av ref0 , av ref1 : analog reference voltage sck0 to sck2: serial clock av ss : analog ground scl0 note 1 : serial clock buz: buzzer clock sda0 note 1 : serial data exa note 2 : external access status output si0 to si2: serial input intp0 to intp6: interrupt from peripherals so0 to so2: serial output nmi: non-maskable interrupt ti00, ti01, p00 to p06: port 0 ti1, ti2, ti5 to ti8: timer input p10 to p17: port 1 to0 to to2, to5 to to8: timer output p20 to p27: port 2 txd1, txd2: transmit data p30 to p37: port 3 v dd : power supply p40 to p47: port 4 v pp : programming power supply p50 to p57: port 5 v ss : ground p60 to p67: port 6 wait: wait p70 to p72: port 7 wr: write strobe p80 to p87: port 8 x1, x2: crystal (main system clock) p90 to p95: port 9 xt1, xt2: crystal (subsystem clock) p100 to p103: port 10 notes 1. the scl0 and sda0 pins are available in the m pd78f4216ay, 78f4218ay only. 2. the exa pin is available in the m pd78f4218a, 78f4218ay only.
data sheet u14125ej1v0ds00 11 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 3. block diagram notes 1. this function supports the i 2 c bus interface and is available in the m pd78f4216ay, 78f4218ay only. 2. the exa pin is available in the m pd78f4218a, 78f4218ay only. intp2/nmi intp0, intp1, intp3 to intp6 programmable interrupt controller real-time output port timer/event counter 7 (8 bits) timer/event counter 6 (8 bits) timer/event counter 5 (8 bits) timer/event counter 2 (8 bits) timer/event counter 1 (8 bits) timer/event counter (16 bits) watch timer timer/event counter 8 (8 bits) watchdog timer ti00 ti01 to0 ti1 to1 ti2 to2 ti5/to5 ti6/to6 ti7/to7 ti8/to8 nmi/intp2 rtp0 to rtp7 clock output control a/d converter av dd av ss pcl buz av ref0 ani0 to ani7 d/a converter ano0 av ss p03/intp3 av ref1 ano1 78k/iv cpu core flash memory ram baud-rate generator rxd1/si1 txd1/so1 asck1/sck1 rxd2/si2 txd2/so2 asck2/sck2 si0/sda0 note 1 so0 sck0/scl0 note 1 bus i/f uart/ioe1 rd astb wr wait a0 to a7 ad0 to ad7 a8 to a15 a16 to a19 port 1 p10 to p17 port 0 p00 to p06 port 2 p20 to p27 port 3 p30 to p37 port 4 p40 to p47 port 5 p50 to p57 port 6 p60 to p67 port 7 p70 to p72 port 8 p80 to p87 port 9 p90 to p95 port 10 p100 to p103 port 12 p120 to p127 port 13 p130, p131 buzzer output system control reset xt2 x1 xt1 x2 v ss v dd v pp clocked serial interface baud-rate generator uart/ioe2 exa note 2
data sheet u14125ej1v0ds00 12 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 4. pin functions 4.1 port pins (1/2) pin name i/o alternate function function p00 intp0 p01 intp1 p02 intp2/nmi p03 intp3 p04 intp4 p05 intp5 p06 i/o intp6 port 0 (p0): 7-bit i/o port input/output can be specified in 1-bit units. whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. p10 to p17 input ani0 to ani7 port 1 (p1): 8-bit input only port p20 rxd1/si1 p21 txd1/so1 p22 asck1/sck1 p23 pcl p24 buz p25 si0/sda0 note 1 p26 so0 p27 i/o sck0/scl0 note 1 port 2 (p2): 8-bit i/o port input/output can be specified in 1-bit units. whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. p30 to0 p31 to1 p32 to2 p33 ti1 p34 ti2 p35 ti00 p36 ti01 p37 i/o exa note 2 port 3 (p3): 8-bit i/o port input/output can be specified in 1-bit units. whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. p40 to p47 i/o ad0 to ad7 port 4 (p4): 8-bit i/o port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. leds can be driven directly. p50 to p57 i/o a8 to a15 port 5 (p5): 8-bit i/o port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. leds can be driven directly. notes 1. this sda0 and scl0 are available in the m pd78f4216ay, 78f4218ay only. 2. this function is available in the m pd78f4218a, 784218ay only.
data sheet u14125ej1v0ds00 13 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 4.1 port pins (2/2) pin name i/o alternate function function p60 a16 p61 a17 p62 a18 p63 a19 p64 rd p65 wr p66 wait p67 i/o astb port 6 (p6): 8-bit i/o port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. p70 rxd2/si2 p71 txd2/so2 p72 i/o asck2/sck2 port 7 (p7): 3-bit i/o port input/output can be specified in 1-bit units. whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. p80 to p87 i/o a0 to a7 port 8 (p8): 8-bit i/o port input/output can be specified in 1-bit units. whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. the interrupt control flag (krif) is set to 1 when a falling edge is detected at a pin of this port. p90 to p95 i/o - port 9 (p9): n-ch open-drain middle-voltage i/o port 6-bit i/o port input/output can be specified in 1-bit units. leds can be driven directly. p100 ti5/to5 p101 ti6/to6 p102 ti7/to7 p103 i/o ti8/to8 port 10 (p10): 4-bit i/o port input/output can be specified in 1-bit units. whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. p120 to p127 i/o rtp0 to rtp7 port 12 (p12): 8-bit i/o port input/output can be specified in 1-bit units. whether specifying input mode or output mode, an on-chip pull-up resistor can be specified in 1-bit units by means of software. p130, p131 i/o ano0, ano1 port 13 (p13): 2-bit i/o port input/output can be specified in 1-bit units.
data sheet u14125ej1v0ds00 14 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 4.2 non-port pins (1/2) pin name i/o alternate function function ti00 p35 external count clock input to 16-bit timer counter ti01 p36 capture trigger signal input to capture/compare register 00 ti1 p33 external count clock input to 8-bit timer counter 1 ti2 p34 external count clock input to 8-bit timer counter 2 ti5 p100/to5 external count clock input to 8-bit timer counter 5 ti6 p101/to6 external count clock input to 8-bit timer counter 6 ti7 p102/to7 external count clock input to 8-bit timer counter 7 ti8 input p103/to8 external count clock input to 8-bit timer counter 8 to0 p30 16-bit timer output (shared by 14-bit pwm output) to1 p31 to2 p32 to5 p100/ti5 to6 p101/ti6 to7 p102/ti7 to8 output p103/ti8 8-bit timer output (shared by 8-bit pwm output) rxd1 p20/si1 serial data input (uart1) rxd2 input p70/si2 serial data input (uart2) txd1 p21/so1 serial data output (uart1) txd2 output p71/so2 serial data output (uart2) asck1 p22/sck1 baud rate clock input (uart1) asck2 input p72/sck2 baud rate clock input (uart2) si0 p25/sda0 note serial data input (3-wire serial i/o 0) si1 p20/rxd1 serial data input (3-wire serial i/o 1) si2 input p70/rxd2 serial data input (3-wire serial i/o 2) so0 p26 serial data output (3-wire serial i/o 0) so1 p21/txd1 serial data output (3-wire serial i/o 1) so2 output p71/txd2 serial data output (3-wire serial i/o 2) sda0 note p25/si0 serial data input/output (i 2 c bus) sck0 p27/scl0 note serial clock input/output (3-wire serial i/o 0) sck1 p22/asck1 serial clock input/output (3-wire serial i/o 1) sck2 p72/asck2 serial clock input/output (3-wire serial i/o 2) scl0 note i/o p27/sck0 serial clock input/output (i 2 c bus) nmi p02/intp2 non-maskable interrupt request input intp0 p00 intp1 p01 intp2 p02/nmi intp3 p03 intp4 p04 intp5 p05 intp6 input p06 external interrupt request input note this function is available in the m pd78f4216ay, 78f4218ay only.
data sheet u14125ej1v0ds00 15 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 4.2 non-port pins (2/2) pin name i/o alternate function function pcl output p23 clock output (for trimming main system clock and sub system clock) buz output p24 buzzer output rtp0 to rtp7 output p120 to p127 real-time output port that outputs data in synchronization with trigger ad0 to ad7 i/o p40 to p47 lower address/data bus for expanding memory externally a0 to a7 p80 to p87 lower address bus for expanding memory externally a8 to a15 p50 to p57 middle address bus for expanding memory externally a16 to a19 output p60 to p63 higher address bus for expanding memory externally rd p64 strobe signal output for reading from external memory wr output p65 strobe signal output for writing to external memory wait input p66 wait insertion at external memory access astb output p67 strobe output that externally latches address information output to ports 4 through 6 and 8 to access external memory exa note output p37 status signal output at external memory access reset input - system reset input x1 input x2 - - connecting crystal resonator for main system clock oscillation xt1 input xt2 - - connecting crystal resonator for sub system clock oscillation ani0 to ani7 input p10 to p17 a/d converter analog input ano0, ano1 output p130, p131 d/a converter analog output av ref0 a/d converter reference voltage input av ref1 d/a converter reference voltage input av dd a/d converter positive power supply. connect to v dd . av ss gnd for a/d converter and d/a converter. connect to v ss . v dd positive power supply v ss gnd v pp -- flash memory programming mode setting. applying high-voltage for program write/verify. connect this pin to v ss directly or via a pull-down resistor in normal operation mode. connect the v pp pin to v ss via a pull-down resistor in a system in which the on-chip flash memory is written while mounted on the target board. for the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 w to 10 k w . note the exa pin is available in the m pd78f4218a, 78f4218ay only.
data sheet u14125ej1v0ds00 16 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 4.3 pin i/o circuits and recommended connections of unused pins the i/o circuit type of each pin and recommended connections of unused pins are shown in table 4-1. for each type of input/output circuit, refer to figure 4-1. table 4-1. types of pin i/o circuits and recommended connection of unused pins (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/intp0 p01/intp1 p02/intp2/nmi p03/intp3 to p06/intp6 8-n i/o input: independently connect to v ss via a resistor output: leave open p10/ani0 to p17/ani7 9 input connect to v ss or v dd p20/rxd1/si1 10-k p21/txd1/so1 10-l p22/asck1/sck1 10-k p23/pcl p24/buz 10-l p25/si0/sda0 note 1 10-k p26/so0 10-l p27/sck0/scl0 note 1 10-k p30/to0 to p32/to2 12-e p33/ti1, p34/ti2 8-n p35/ti00, p36/ti01 10-m p37/exa note 2 12-e p40/ad0 to p47/ad7 p50/a8 to p57/a15 p60/a16 to p63/a19 p64/rd p65/wr p66/wait p67/astb 5-a p70/rxd2/si2 8-n p71/txd2/so2 10-m p72/asck2/sck2 8-n p80/a0 to p87/a7 12-e p90 to p95 13-d p100/ti5/to5 p101/ti6/to6 p102/ti7/to7 p103/ti8/to8 8-n p120/rtp0 to p127/rtp7 12-e p130/ano0, p131/ano1 12-f i/o input: independently connect to v ss via a resistor output: leave open notes 1. the sda0 and scl0 pins are available in the m pd78f4216ay, 78f4218ay only. 2. the exa pin is available in the m pd78f4218a, 78f4218ay only.
data sheet u14125ej1v0ds00 17 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay table 4-1. types of pin i/o circuits and recommended connection of unused pins (2/2) pin name i/o circuit type i/o recommended connection of unused pins reset 2-g - xt1 input connect to v ss xt2 16 leave open av ref0 connect to v ss av ref1 av dd connect to v dd av ss connect to v ss v pp - - connect this pin to v ss directly or via a pull-down resist in normal operation mode. connect the v pp pin to v ss via a pull-down resistor in a system in which the on-chip flash memory is written while mounted on the target board. for the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 w to 10 k w . remark because the circuit type numbers are standardized among the 78k series products, they are not sequential in some models (i.e., some circuits are not provided).
data sheet u14125ej1v0ds00 18 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay figure 4-1. types of pin i/o circuits (1/2) in pullup enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch pullup enable data output disable v dd p-ch v dd p-ch in/out n-ch pullup enable data open drain output disable v dd p-ch v dd p-ch in/out n-ch pullup enable data open drain output disable output disable v dd p-ch v dd v ss p-ch in/out n-ch pullup enable data v dd p-ch v dd v ss p-ch in/out n-ch pullup enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch p-ch n-ch in comparator + C p-ch n-ch input enable type 2-g type 5-a type 8-n type 9 (threshold voltage) analog output voltage type 12-e type 10-m type 10-l type 10-k schmitt-triggered input with hysteresis characteristics v ref
data sheet u14125ej1v0ds00 19 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay figure 4-1. types of pin i/o circuits (2/2) data output disable middle-voltage input buffer in/out n-ch p-ch v dd rd data analog output voltage type 12-f type 13-d type 16 output disable p-ch in/out v dd v ss v ss n-ch input enable p-ch n-ch p-ch feedback cut-off xt1 xt2
data sheet u14125ej1v0ds00 20 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 5. internal memory size switching register (ims) ims is a register that is set by software and is used to specify a part of the internal memory that is not to be used. by setting this register, the internal memory of the m pd78f4218ay can be mapped identically to that of a mask rom version with a different internal memory (rom and ram) capacity. ims is set with an 8-bit memory manipulation instruction. reset input sets ims to ffh. (1) m m m m pd78f4216a, 78f4216ay figure 5-1. internal memory size switching register (ims) format address: 0fffch after reset: ffh w 76543210 ims 1 1 rom1 rom0 1 1 ram1 ram0 rom1 rom0 internal rom capacity selection 0 0 48 kb 0 1 64 kb 1 0 96 kb 1 1 128 kb ram1 ram0 peripheral ram capacity selection 0 0 3,072 bytes 0 1 4,608 bytes 1 0 6,114 bytes 1 1 7,680 bytes caution ims is not provided on the mask rom versions ( m m m m pd784214a, 784215a, 784216a, m m m m pd784214ay, 784215ay, and 784216ay). table 5-1 shows the ims setting values to make the memory mapping the same as that of the mask rom versions. table 5-1. setting value of internal memory size switching register (ims) target mask rom version ims setting value m pd784214a, 784214ay ech m pd784215a, 784215ay fdh m pd784216a, 784216ay ffh
data sheet u14125ej1v0ds00 21 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay (2) m m m m pd78f4218a, 78f4218ay figure 5-2. internal memory size switching register (ims) format address: 0fffch after reset: ffh w 76543210 ims 1 1 rom1 rom0 1 1 ram1 ram0 rom1 rom0 internal rom capacity selection 0 0 64 kb 0 1 128 kb 1 0 192 kb 1 1 256 kb ram1 ram0 peripheral ram capacity selection 0 0 3,072 bytes 0 1 6,656 bytes 1 0 7,168 bytes 1 1 12,288 bytes caution ims is not provided on the mask rom versions ( m m m m pd784217a, 784218a, 784217ay, and 784218ay). table 5-2 shows the ims setting values to make the memory mapping the same as that of the mask rom versions. table 5-2. setting value of internal memory size switching register (ims) target mask rom version ims setting value m pd784217a, 784217ay efh m pd784218a, 784218ay ffh
data sheet u14125ej1v0ds00 22 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 6. programming flash memory the flash memory can be written with the m pd78f4218ay mounted on the target board (on-board). to do so, connect a dedicated flash programmer (flashpro ii (part number: fl-pr2), flashpro iii (part number: fl-pr3, pg- fp3) to the host machine and target system. writing to flash memory can also be performed using flash memory writing adapter connected to flashpro ii or flashpro iii. remark fl-pr2 and fl-pr3 are products of naito densei machida mfg. co., ltd. 6.1 selecting communication mode to write the flash memory, use flashpro ii and flashpro iii by serial communication. select a serial communication mode from those listed in table 6-1 in the format shown in figure 6-1. each communication mode is selected by the number of v pp pulses shown in table 6-1. table 6-1. communication modes communication mode number of channels pins used number of v pp pulses sck0/p27/scl0 note 1 so0/p26 si0/p25/sda0 note 1 0 sck1/asck1/p22 so1/txd1/p21 si1/rxd1/p20 1 3-wire serial i/o 3 sck2/asck2/p72 so2/txd2/p71 si2/rxd2/p70 2 handshake note 2 1 sck0/p27/scl0 note 1 so0/p26 si0/p25/sda0 note 1 p24/buz 3 txd1/so1/p21 rxd1/si1/p20 8 uart 2 txd2/so2/p71 rxd2/si2/p70 9 notes 1. the scl0 and sda0 pins are available in the m pd78f4216ay, 78f4218ay only. 2. this made is available in the m pd78f4216a, 78f4216ay (other than i, k, e standard) this made is available in the m pd78f4218a, 78f4218ay (other than i standard) caution be sure to select a communication mode with the number of v pp pulses shown in table 6-1.
data sheet u14125ej1v0ds00 23 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay figure 6-1. communication mode selecting format 6.2 flash memory programming function the flash memory is written by transferring or receiving commands and data in a selected communication mode. the major functions of flash memory programming are listed in table 6-2. table 6-2. major functions of flash memory programming function description batch erasure erases all contents of memory. block erasure erases contents of specified memory block with one memory block consisting of 16 kb. batch blank check checks erased status of entire memory. block blank check checks erased status of specified block. data write writes flash memory based on write start address and number of data to be written (in bytes). batch verify compares all contents of memory with input data. block verify compares contents of specified memory block with input data. 10 v v dd v ss v dd v pp reset v ss 12 n v pp pulses flash programming mode
data sheet u14125ej1v0ds00 24 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 6.3 connecting flashpro ii and flashpro iii the flashpro ii, flashpro iii and m pd78f4218ay are connected differently depending on the selected communication mode (3-wire serial i/o or uart). figures 6-2 to 6-4 show the connections in the respective communication modes. figure 6-2. connection of flashpro ii and flashpro iii in 3-wire serial i/o mode figure 6-3. connection of flashpro iii in handshake mode figure 6-4. connection of flashpro ii and flashpro iii in uart mode v pp v dd reset sck0 or sck1 or sck2 si0 or si1 or si2 so0 or so1 or so2 v ss flashpro ll, flashpro lll pd78f4218ay m v pp v dd reset sck0 si0 so0 p24 v ss flashpro lll pd78f4218ay m v pp v dd reset rxd1 or rxd2 txd1 or txd2 v ss flashpro ll, flashpro lll pd78f4218ay m
data sheet u14125ej1v0ds00 25 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 7. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd - 0.3 to +6.5 v av dd - 0.3 to v dd + 0.3 v av ss - 0.3 to v ss + 0.3 v av ref0 a/d converter reference voltage input - 0.3 to v dd + 0.3 v supply voltage av ref1 d/a converter reference voltage input - 0.3 to v dd + 0.3 v v i1 other than p90 to p95 - 0.3 to v dd + 0.3 v v i2 p90 to p95 n-ch open drain - 0.3 to +12 v input voltage v i3 v pp pin for programming - 0.3 to +10.5 v analog input voltage v an analog input pin av ss - 0.3 to av ref0 + 0.3 v output voltage v o - 0.3 to v dd + 0.3 v per pin 15 ma total of p2, p4 to p8 75 ma total of p0, p3, p9, p10, p12, p13 75 ma output current, low i ol total of all pins 100 ma per pin - 10 ma output current, high i oh total of all pins - 50 ma operating ambient temperature t a - 40 to +85 c storage temperature t stg - 65 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
data sheet u14125ej1v0ds00 26 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay operating conditions operating ambient temperature (t a ): - 40 to +85 c supply voltage and clock cycle time: see figure 7-1 operating voltage with subsystem clock operation: v dd = 1.9 to 5.5 v figure 7-1. supply voltage and clock cycle time (cpu clock frequency: f cpu ) capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit other than port 9 15 pf input capacitance c i port 9 20 pf other than port 9 15 pf output capacitance c o port 9 20 pf other than port 9 15 pf i/o capacitance c io f = 1 mhz unmeasured pins returned to 0 v. port 9 20 pf 8,000 10,000 500 400 300 320 160 80 200 100 0 0123 1.9 2.7 4.5 5.5 supply voltage [v] 456 clock cycle time t cyk [ns] guaranteed operating range
data sheet u14125ej1v0ds00 27 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay main system clock oscillator characteristics (t a = - - - - 40 to +85 c) resonator recommended circuit parameter conditions min. typ. max. unit 4.5 v v dd 5.5 v 2 12.5 2.7 v v dd < 4.5 v 2 6.25 2.0 v v dd < 2.7 v 2 3.125 ceramic resonator or crystal resonator x2 x1 v ss oscillation frequency (f x ) 1.9 v v dd < 2.0 v 2 2 mhz 4.5 v v dd 5.5 v 2 12.5 2.7 v v dd < 4.5 v 2 6.25 2.0 v v dd < 2.7 v 2 3.125 x1 input frequency (f x ) 1.9 v v dd < 2.0 v 2 2 mhz x1 input high-/low- level width (t wxh , t wxl ) 15 250 ns 4.5 v v dd 5.5 v 0 5 2.7 v v dd < 4.5 v 0 10 2.0 v v dd < 2.7 v 0 20 external clock x2 x1 pd74hcu04 m x1 input rising/falling time (t xr , t xf ) 1.9 v v dd < 2.0 v 0 30 ns cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched back to the main system clock after the oscillation stabilization time is secured by the program. remark for the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
data sheet u14125ej1v0ds00 28 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay subsystem clock oscillator characteristics (t a = - - - - 40 to +85 c) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) 32 32.768 35 khz 4.5 v v dd 5.5 v 1.2 2 crystal resonator v ss xt2 xt1 oscillation stabilization time note 1.9 v v dd < 4.5 v 10 s xt1 input frequency (f xt ) 32 35 khz external clock xt2 xt1 pd74hcu04 m xt1 input high-/low- level width (t xth , t xtl ) 14.3 15.6 m s note time required to stabilize oscillation after applying supply voltage (v dd ). cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
data sheet u14125ej1v0ds00 29 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay dc characteristics (t a = - - - - 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) (1/3) parameter symbol conditions min. typ. max. unit 2.2 v v dd 5.5 v 0 0.3v dd v il1 note 1 1.9 v v dd < 2.2 v 0 0.2v dd v 2.2 v v dd 5.5 v 0 0.2v dd v il2 p00 to p06, p20, p22, p33, p34, p70, p72, p100 to p103, reset 1.9 v v dd < 2.2 v 0 0.15v dd v 2.2 v v dd 5.5 v 0 0.3v dd v il3 p90 to p95 (n-ch open drain) 1.9 v v dd < 2.2 v 0 0.2v dd v 2.2 v v dd 5.5 v 0 0.3v dd v il4 p10 to p17, p130, p131 1.9 v v dd < 2.2 v 0 0.2v dd v 2.2 v v dd 5.5 v 0 0.2v dd v il5 x1, x2, xt1, xt2 1.9 v v dd < 2.2 v 0 0.1v dd v 2.2 v v dd 5.5 v 0 0.3v dd input voltage, low v il6 p25, p27 1.9 v v dd < 2.2 v 0 0.2v dd v 2.2 v v dd 5.5 v 0.7v dd v dd v ih1 note 1 1.9 v v dd < 2.2 v 0.8v dd v dd v 2.2 v v dd 5.5 v 0.8v dd v dd v ih2 p00 to p06, p20, p22, p33, p34, p70, p72, p100 to p103, reset 1.9 v v dd < 2.2 v 0.85v dd v dd v 2.2 v v dd 5.5 v 0.7v dd 12 v ih3 p90 to p95 (n-ch open drain) 1.9 v v dd < 2.2 v 0.8v dd v dd v 2.2 v v dd 5.5 v 0.7v dd v dd v ih4 p10 to p17, p130, p131 1.9 v v dd < 2.2 v 0.8v dd v dd v 2.2 v v dd 5.5 v 0.8v dd v dd v ih5 x1, x2, xt1, xt2 1.9 v v dd < 2.2 v 0.85v dd v dd v 2.2 v v dd 5.5 v 0.7v dd v dd input voltage, high v ih6 p25, p27 1.9 v v dd < 2.2 v 0.8v dd v dd v for pins other than p40 to p47, p50 to p57, p90 to p95 i ol = 1.6 ma note 1 4.5 v v dd 5.5 v 0.4 v p40 to p47, p50 to p57 i ol = 8 ma note 2 4.5 v v dd 5.5 v 1.0 v v ol1 p90 to p95 i ol = 15 ma note 2 4.5 v v dd 5.5 v 0.8 2.0 v output voltage, low v ol2 i ol = 400 m a note 2 0.5 v i oh = - 1 ma note 2 4.5 v v dd 5.5 v v dd - 1.0 v output voltage, high v oh1 i ol = - 100 m a note 2 v dd - 0.5 v i lil1 except x1, x2, xt1 , xt2 - 3 m a input leakage current, low i lil2 v in = 0 v x1, x2, xt1, xt2 - 20 m a i lih1 except x1, x2, xt1 , xt2 3 m a i lih2 v in = v dd x1, x2, xt1, xt2 20 m a input leakage current, high i lih3 v in = 12 v (n-ch open drain) p90 to p95 20 m a output leakage current, low i lol1 v out = 0 v - 3 m a output leakage current, high i loh1 v out = v dd 3 m a notes 1. p21, p23, p24, p26, p30 to p32, p35 to p37, p40 to p47, p50 to p57, p60 to p67, p71, p80 to p87, p120 to p127 2. per pin
data sheet u14125ej1v0ds00 30 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay dc characteristics (t a = - - - - 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) (2/3) (1) m m m m pd78f4216a, 78f4216ay parameter symbol conditions min. typ. max. unit f xx = 12.5 mhz, v dd = 5.0 v 10% 17 40 ma f xx = 6 mhz, v dd = 3.0 v 10% 5 17 ma i dd1 operation mode f xx = 2 mhz, v dd = 2.0 v 5% 2 10 ma f xx = 12.5 mhz, v dd = 5.0 v 10% 6 20 ma f xx = 6 mhz, v dd = 3.0 v 10% 2 10 ma i dd2 halt mode f xx = 2 mhz, v dd = 2.0 v 5% 0.4 7 ma f xx = 12.5 mhz, v dd = 5.0 v 10% 1 3 ma f xx = 6 mhz, v dd = 3.0 v 10% 0.5 1.3 ma i dd3 idle mode f xx = 2 mhz, v dd = 2.0 v 5% 0.3 0.9 ma f xx = 32 khz, v dd = 5.0 v 10% 130 500 m a f xx = 32 khz, v dd = 3.0 v 10% 90 350 m a f xx = 32 khz, 2.0 v v dd 2.7 v 80 300 m a i dd4 operation mode note f xx = 32 khz, 1.9 v v dd < 2.0 v 70 250 m a f xx = 32 khz, v dd = 5.0 v 10% 60 200 m a f xx = 32 khz, v dd = 3.0 v 10% 20 160 m a f xx = 32 khz, 2.0 v v dd 2.7 v 15 120 m a i dd5 halt mode note f xx = 32 khz, 1.9 v v dd < 2.0 v 10 100 m a f xx = 32 khz, v dd = 5.0 v 10% 50 190 m a f xx = 32 khz, v dd = 3.0 v 10% 15 150 m a f xx = 32 khz, 2.0 v v dd 2.7 v 12 110 m a supply voltage i dd6 idle mode note f xx = 32 khz, 1.9 v v dd < 2.0 v 7 90 m a data retention voltage v dddr halt, idle modes 1.9 5.5 v v dd = 2.0 v 5% 2 10 m a data retention current i dddr stop mode v dd = 5.0 v 10% 10 50 m a pull-up resistor r l v in = 0 v 10 30 100 k w note when main system clock is stopped and subsystem clock is operating. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
data sheet u14125ej1v0ds00 31 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay dc characteristics (t a = - - - - 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) (3/3) (2) m m m m pd78f4218a, 78f4218ay parameter symbol conditions min. typ. max. unit f xx = 12.5 mhz, v dd = 5.0 v 10% 19 40 ma f xx = 6 mhz, v dd = 3.0 v 10% 6 17 ma i dd1 operation mode f xx = 3 mhz, v dd = 2.0 v 5% 2 10 ma f xx = 12.5 mhz, v dd = 5.0 v 10% 7 20 ma f xx = 6 mhz, v dd = 3.0 v 10% 2 10 ma i dd2 halt mode f xx = 3 mhz, v dd = 2.0 v 5% 0.5 7 ma f xx = 12.5 mhz, v dd = 5.0 v 10% 1 3 ma f xx = 6 mhz, v dd = 3.0 v 10% 0.5 1.3 ma i dd3 idle mode f xx = 3 mhz, v dd = 2.0 v 5% 0.3 0.9 ma f xx = 32 khz, v dd = 5.0 v 10% 140 500 m a f xx = 32 khz, v dd = 3.0 v 10% 100 350 m a f xx = 32 khz, 2.0 v v dd 2.7 v 90 300 m a i dd4 operation mode note f xx = 32 khz, 1.9 v v dd < 2.0 v 80 250 m a f xx = 32 khz, v dd = 5.0 v 10% 60 200 m a f xx = 32 khz, v dd = 3.0 v 10% 20 160 m a f xx = 32 khz, 2.0 v v dd 2.7 v 15 120 m a i dd5 halt mode note f xx = 32 khz, 1.9 v v dd < 2.0 v 10 100 m a f xx = 32 khz, v dd = 5.0 v 10% 50 190 m a f xx = 32 khz, v dd = 3.0 v 10% 15 150 m a f xx = 32 khz, 2.0 v v dd 2.7 v 12 110 m a supply voltage i dd6 idle mode note f xx = 32 khz, 1.9 v v dd < 2.0 v 7 90 m a data retention voltage v dddr halt, idle modes 1.9 5.5 v v dd = 2.0 v 5% 2 10 m a data retention current i dddr stop mode v dd = 5.0 v 10% 10 50 m a pull-up resistor r l v in = 0 v 10 30 100 k w note when main system clock is stopped and subsystem clock is operating. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
data sheet u14125ej1v0ds00 32 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay ac characteristics (t a = - - - - 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) (1) read/write operation (1/2) parameter symbol conditions min. typ. max. unit 4.5 v v dd 5.5 v 80 ns 2.7 v v dd < 4.5 v 160 ns 2.0 v v dd < 2.7 v 320 ns cycle time t cyk 1.9 v v dd < 2.0 v 500 ns v dd = 5.0 v 10% (0.5 + a)t - 20 ns v dd = 3.0 v 10% (0.5 + a)t - 40 ns address setup time (to astb )t sast v dd = 2.0 v 5% (0.5 + a)t - 80 ns v dd = 5.0 v 10% 0.5t - 19 ns v dd = 3.0 v 10% 0.5t - 24 ns address hold time (from astb )t hstla v dd = 2.0 v 5% 0.5t - 34 ns v dd = 5.0 v 10% (0.5 + a)t - 17 ns v dd = 3.0 v 10% (0.5 + a)t - 40 ns astb high-level width t wsth v dd = 2.0 v 5% (0.5 + a)t - 110 ns v dd = 5.0 v 10% 0.5t - 14 ns v dd = 3.0 v 10% 0.5t - 14 ns address hold time (from rd - )t hra v dd = 2.0 v 5% 0.5t - 14 ns v dd = 5.0 v 10% (1 + a)t - 24 ns v dd = 3.0 v 10% (1 + a)t - 35 ns delay time from address to rd t dar v dd = 2.0 v 5% (1 + a)t - 80 ns v dd = 5.0 v 10% 0 ns v dd = 3.0 v 10% 0 ns address float time (from rd )t far v dd = 2.0 v 5% 0 ns v dd = 5.0 v 10% (2.5 + a + n)t - 37 ns v dd = 3.0 v 10% (2.5 + a + n)t - 52 ns data input time from address t daid v dd = 2.0 v 5% (2.5 + a + n)t - 120 ns v dd = 5.0 v 10% (2 + n)t - 35 ns v dd = 3.0 v 10% (2 + n)t - 50 ns data input time from astb t dstid v dd = 2.0 v 5% (2 + n)t - 80 ns v dd = 5.0 v 10% (1.5 + n)t - 40 ns v dd = 3.0 v 10% (1.5 + n)t - 50 ns data input time from rd t drid v dd = 2.0 v 5% (1.5 + n)t - 90 ns v dd = 5.0 v 10% 0.5t - 9ns v dd = 3.0 v 10% 0.5t - 9ns delay time from astb to rd t dstr v dd = 2.0 v 5% 0.5t - 20 ns v dd = 5.0 v 10% 0 ns v dd = 3.0 v 10% 0 ns data hold time (from rd - )t hrid v dd = 2.0 v 5% 0 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of waits (n 3 0)
data sheet u14125ej1v0ds00 33 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay ac characteristics (1) read/write operation (2/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% 0.5t - 2ns v dd = 3.0 v 10% 0.5t - 12 ns address active time from rd - t dra v dd = 2.0 v 5% 0.5t - 35 ns v dd = 5.0 v 10% 0.5t - 9ns v dd = 3.0 v 10% 0.5t - 9ns delay time from rd - to astb - t drst v dd = 2.0 v 5% 0.5t - 40 ns v dd = 5.0 v 10% (1.5 + n)t - 25 ns v dd = 3.0 v 10% (1.5 + n)t - 30 ns rd low-level width t wrl v dd = 2.0 v 5% (1.5 + n)t - 25 ns v dd = 5.0 v 10% (1 + a)t - 24 ns v dd = 3.0 v 10% (1 + a)t - 34 ns delay time from address to wr t daw v dd = 2.0 v 5% (1 + a)t - 70 ns v dd = 5.0 v 10% 0.5t - 14 ns v dd = 3.0 v 10% 0.5t - 14 ns address hold time (from wr - )t hrd v dd = 2.0 v 5% 0.5t - 14 ns v dd = 5.0 v 10% 0.5t + 15 ns v dd = 3.0 v 10% 0.5t + 30 ns delay time from astb to data output t dstod v dd = 2.0 v 5% 0.5t + 240 ns v dd = 5.0 v 10% 0.5t - 30 ns v dd = 3.0 v 10% 0.5t - 30 ns delay time from wr to data output t dwod v dd = 2.0 v 5% 0.5t - 30 ns v dd = 5.0 v 10% 0.5t - 9ns v dd = 3.0 v 10% 0.5t - 9ns delay time from astb to wr t dstw v dd = 2.0 v 5% 0.5t - 20 ns v dd = 5.0 v 10% (1.5 + n)t - 20 ns v dd = 3.0 v 10% (1.5 + n)t - 25 ns data setup time (to wr - )t sodwr v dd = 2.0 v 5% (1.5 + n)t - 70 ns v dd = 5.0 v 10% 0.5t - 14 ns v dd = 3.0 v 10% 0.5t - 14 ns data hold time (from wr - )t hwod v dd = 2.0 v 5% 0.5t - 50 ns v dd = 5.0 v 10% 0.5t - 9ns v dd = 3.0 v 10% 0.5t - 9ns delay time from wr - to astb - t dwst v dd = 2.0 v 5% 0.5t - 30 ns v dd = 5.0 v 10% (1.5 + n)t - 25 ns v dd = 3.0 v 10% (1.5 + n)t - 30 ns wr low-level width t wwl v dd = 2.0 v 5% (1.5 + n)t - 30 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 3 0)
data sheet u14125ej1v0ds00 34 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay ac characteristics (2) external wait timing parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% (2 + a)t - 40 ns v dd = 3.0 v 10% (2 + a)t - 60 ns input time from address to wait t dawt v dd = 2.0 v 5% (2 + a)t - 300 ns v dd = 5.0 v 10% 1.5t - 40 ns v dd = 3.0 v 10% 1.5t - 60 ns input time from astb to wait t dstwt v dd = 2.0 v 5% 1.5t - 260 ns v dd = 5.0 v 10% (0.5 + n)t + 5ns v dd = 3.0 v 10% (0.5 + n)t + 10 ns hold time from astb to wait t hstwt v dd = 2.0 v 5% (0.5 + n)t + 30 ns v dd = 5.0 v 10% (1.5 + n)t - 40 ns v dd = 3.0 v 10% (1.5 + n)t - 60 ns delay time from astb to wait - t dstwth v dd = 2.0 v 5% (1.5 + n)t - 90 ns v dd = 5.0 v 10% t - 40 ns v dd = 3.0 v 10% t - 60 ns input time from rd to wait t drwtl v dd = 2.0 v 5% t - 70 ns v dd = 5.0 v 10% nt + 5ns v dd = 3.0 v 10% nt + 10 ns hold time from rd to wait t hrwt v dd = 2.0 v 5% nt + 30 ns v dd = 5.0 v 10% (1 + n)t - 40 ns v dd = 3.0 v 10% (1 + n)t - 60 ns delay time from rd to wait - t drwth v dd = 2.0 v 5% (1 + n)t - 90 ns v dd = 5.0 v 10% 0.5t - 5ns v dd = 3.0 v 10% 0.5t - 10 ns data input time from wait - t dwtid v dd = 2.0 v 5% 0.5t - 30 ns v dd = 5.0 v 10% 0.5t ns v dd = 3.0 v 10% 0.5t ns delay time from wait - to rd - t dwtr v dd = 2.0 v 5% 0.5t + 5ns v dd = 5.0 v 10% 0.5t ns v dd = 3.0 v 10% 0.5t ns delay time from wait - to wr - t dwtw v dd = 2.0 v 5% 0.5t + 5ns v dd = 5.0 v 10% t - 40 ns v dd = 3.0 v 10% t - 60 ns input time from wr to wait t dwwtl v dd = 2.0 v 5% t - 90 ns v dd = 5.0 v 10% nt + 5ns v dd = 3.0 v 10% nt + 10 ns hold time from wr to wait t hwwt v dd = 2.0 v 5% nt + 30 ns v dd = 5.0 v 10% (1 + n)t - 40 ns v dd = 3.0 v 10% (1 + n)t - 60 ns delay time from wr to wait - t dwwth v dd = 2.0 v 5% (1 + n)t - 90 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 3 0)
data sheet u14125ej1v0ds00 35 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay serial operation (t a = - - - - 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) (a) 3-wire serial i/o mode (sck: internal clock output) parameter symbol conditions min. typ. max. unit 2.7 v v dd 5.5 v 800 ns sck cycle time t kcy1 3,200 ns 2.7 v v dd 5.5 v 350 ns sck high-/low-level width t kh1 , t kl1 1,500 ns 2.7 v v dd 5.5 v 10 ns si setup time (to sck - )t sik1 30 ns si hold time (from sck - )t ksi1 40 ns so output delay time (from sck ) t kso1 30 ns (b) 3-wire serial i/o mode (sck: external clock input) parameter symbol conditions min. typ. max. unit 2.7 v v dd 5.5 v 800 ns sck cycle time t kcy2 3,200 ns 2.7 v v dd 5.5 v 400 ns sck high-/low-level width t kh2 t kl2 1,600 ns 2.7 v v dd 5.5 v 10 ns si setup time (to sck - )t sik2 30 ns si hold time (from sck - )t ksi2 40 ns so output delay time (from sck ) t kso2 30 ns (c) uart mode parameter symbol conditions min. typ. max. unit 4.5 v v dd 5.5 v 417 ns 2.7 v v dd < 4.5 v 833 ns asck cycle time t kcy3 1,667 ns 4.5 v v dd 5.5 v 208 ns 2.7 v v dd < 4.5 v 416 ns asck high-/low-level width t kh3 t kl3 833 ns
data sheet u14125ej1v0ds00 36 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay (d) i 2 c bus mode standard mode high-speed mode parameter symbol min. max. min. max. unit scl0 clock frequency f clk 0 100 0 400 khz bus free time (between stop and start conditions) t buf 4.7 - 1.3 - m s hold time note1 t hd : sta 4.0 - 0.6 - m s low-level width of scl0 clock t low 4.7 - 1.3 - m s high-level width of scl0 clock t high 4.0 - 0.6 - m s setup time of start/restart conditions t su : sta 4.7 - 0.6 - m s when using cbus- compatible master 5.0 --- m s data hold time when using i 2 c bus t hd : dat 0 note 2 - 0 note 2 0.9 note 3 m s data setup time t su : dat 250 - 100 note 4 - ns rise time of sda0 and scl0 signals t r - 1,000 20 + 0.1cb note 5 300 ns fall time of sda0 and scl0 signals t f - 300 20 + 0.1cb note 5 300 ns setup time of stop condition t su : sto 4.0 - 0.6 - m s pulse width of spike restricted by input filter t sp -- 050ns load capacitance of each bus line cb - 400 - 400 pf notes 1. for the start condition, the first clock pulse is generated after the hold time. 2. to fill the undefined area of the scl0 falling edge, it is necessary for the device to provide an internal sda0 signal (on v ihmin. ) with at least 300 ns of hold time. 3. if the device does not extend the scl0 signal low-level hold time (t low ), only the maximum data hold time t hd : dat needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in a standard mode i 2 c bus system. in this case, the conditions described below must be satisfied. if the device does not extend the scl0 signal low-level hold time t su : dat 3 250 ns if the device extends the scl0 signal low-level hold time be sure to transmit the data bit to the sda0 line before the scl0 line is released (t rmax. + t su : dat = 1,000 + 250 = 1,250 ns by standard mode i 2 c bus specification) 5. cb: total capacitance per bus line (unit: pf)
data sheet u14125ej1v0ds00 37 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay other operations (t a = - - - - 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit nmi high-/low-level width t wnil t wnih 10 m s interrupt input high-/low-level width t witl t with intp0 to intp6 100 ns reset high-/low-level width t wrsl t wrsh 10 m s clock output operation (t a = - - - - 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit pcl cycle time t cycl 4.5 v v dd 5.5 v, nt 80 31,250 ns pcl high-/low-level width t cll t clh 4.5 v v dd 5.5 v, 0.5t - 10 30 15,615 ns 4.5 v v dd 5.5 v 5 ns 2.7 v v dd < 4.5 v 10 ns pcl rise/fall time t clr t clf 1.9 v v dd < 2.7 v 20 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) n: divided frequency ratio set by software in the cpu when using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128 when using the subsystem clock: n = 1
data sheet u14125ej1v0ds00 38 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay a/d converter characteristics (t a = - - - - 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bits 2.7 v v dd 5.5 v 2.2 v av ref0 v dd 1.2 %fsr overall error notes 1, 2 1.9 v v dd < 2.7 v 1.9 v av ref0 v dd 1.6 %fsr conversion time t conv 14 144 m s sampling time t samp 24/f xx m s analog input voltage v ian av ss av ref0 v reference voltage av ref0 1.9 av dd v resistance between av ref0 and av ss r avref0 when not a/d converting 40 k w notes 1. quantization error ( 1/2 lsb) is not included. 2. overall error is indicated as a ratio to the full-scale value. remark f xx : main system clock frequency d/a converter characteristics (t a = - - - - 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bits r = 10 m w , 2.0 v av ref1 v dd , 2.0 v v dd 5.5 v 0.6 %fsr overall error notes 1, 2 r = 10 m w , 1.9 v av ref1 v dd , 1.9 v v dd 2.0 v 1.2 %fsr 4.5 v av ref1 5.5 v 10 m s 2.7 v av ref1 < 4.5 v 15 m s settling time load conditions: c = 30 pf 1.9 v av ref1 < 2.7 v 20 m s output resistance r o dacs0, 1 = 55h 8 k w reference voltage av ref1 1.9 v dd v av ref1 current ai ref1 for only 1 channel 2.5 ma notes 1. quantization error ( 1/2 lsb) is not included. 2. overall error is indicated as a ratio to the full-scale value.
data sheet u14125ej1v0ds00 39 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay data retention characteristics (t a = - - - - 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 1.9 5.5 v v dddr = 5.0 v 10% 10 50 m a data retention current i dddr v dddr = 2.0 v 5% 2 10 m a v dd rise time t rvd 200 m s v dd fall time t fvd 200 m s v dd hold time (from stop mode setting) t hvd 0ms stop release signal input time t drel 0ms crystal resonator 30 ms oscillation stabilization wait time t wait ceramic resonator 5 ms low-level input voltage v il 00.1v dddr v high-level input voltage v ih reset, p00/intp0 to p06/intp6 0.9v dddr v dddr v ac timing test points 0.8v dd or 1.9 v 0.8 v 0.8v dd or 1.9 v 0.8 v test points v dd - 1 v 0.45 v
data sheet u14125ej1v0ds00 40 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay timing waveforms (1) read operations remark the signal is output from pins a0 to a7 when p80 to p87 are unused. (clk) a8 to a19 (output) astb (output) rd (output) wait (input) ad0 to ad7 (i/o) t cyk higher address hi-z hi-z hi-z higher address a0 to a7 (output) lower address lower address data (input) lower address (output) lower address (output) t daid t hra t sast t wsth t dstr t drst t dar t drid t wrl t drwth t dstwt t dstwth t hstwt t hrwt t dawt t dwtr t hstla t far t dwtid t drwtl t hrid t dra t dstid
data sheet u14125ej1v0ds00 41 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay (2) write operation remark the signal is output from pins a0 to a7 when p80 to p87 are unused. (clk) a8 to a19 (output) astb (output) wait (input) ad0 to ad7 (output) t cyk t daid t hwa t sast t wsth t dstw t dwst t daw t dwod t wwl t dwwth t dstwt t dstwth t hstwt t hwwt t dawt t dwtw t hstla t far t dwtid t dwwtl t hwod t daw t dstod t sodwr hi-z hi-z hi-z wr (output) higher address higher address a0 to a7 (output) lower address lower address data (output) lower address (output) lower address (output)
data sheet u14125ej1v0ds00 42 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay serial operation (1) 3-wire serial i/o mode (2) uart mode (3) i 2 c bus mode ( m m m m pd78f4216ay, 78f4218ay only) sck si/so t kcy1, 2 t kl1, 2 t kh1, 2 t kso1, 2 t sik1, 2 t ksi1, 2 asck t kcy3 t kh3 t kl3 scl0 sda0 t r t hd : dat t hd : sta t buf t high t su : dat t f t su : sta t hd : sta t sp t su : sto stop condition start condition restart condition stop condition
data sheet u14125ej1v0ds00 43 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay clock output timing interrupt input timing reset input timing clkout t clh t cll t cycl t clf t clr nmi intp0 to intp6 t wnih t wnil t with t witl reset t wrsh t wrsl
data sheet u14125ej1v0ds00 44 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay clock timing data retention characteristics x1 t wxh t wxl 1/f x t xf t xr xt1 t xth t xtl 1/f xt v dd reset nmi (cleared by falling edge) nmi (cleared by rising edge) t hvd t fvd t rvd t drel v dddr stop mode setting t wait
data sheet u14125ej1v0ds00 45 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay flash memory programming characteristics (v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v, v pp = 9.7 to 10.3 v) (1) basic characteristics parameter symbol conditions min. typ. max. unit 4.5 v v dd 5.5 v 2 12.5 mhz 2.7 v v dd < 4.5 v 2 6.25 mhz 2.0 v v dd < 2.7 v 2 3.125 mhz operating frequency f x 1.9 v v dd < 2.0 v 2 2 2 mhz v dd 1.9 5.5 v v ppl upon v pp low-level detection 0 0.2v dd v v pp upon v pp high-level detection 0.9v dd v dd 1.1v dd v supply voltage note 1 v pph upon v pp high-voltage detection 9.7 10 10.3 v v dd supply current i dd 40 ma v pp supply current i pp v pp = 10 v 100 ma write count c wrt 20 note2 times operating temperature note 3 t a - 40 85 c storage temperature note 4 t stg - 65 125 c programming temperature t prg 10 40 c notes 1. m pd78f4216a, 78f4216ay k standard: 2.7 v v dd < 5.5 v, v pp = 10.3 0.3 v e standard: 2.7 v v dd < 5.5 v, v pp = 10.0 0.3 v 2. operation cannot be guaranteed when the number of writes exceeds 20 times. in the case of the m pd78f4216a and 78f4216ay with k standard, operation cannot be guaranteed when the number of writes exceeds 5 times. 3. m pd78f4216a, 78f4216ay k standard: t a = - 10 to +60 c 4. m pd78f4216a, 78f4216ay k standard: t a = - 10 to +80 c cautions 1. if writing is not successful in write operation, execute the program command again, and execute the verify command to confirm the normal completion of the write operation. ( m m m m pd78f4216a, 78f4216ay: i, k, e, p standard) 2. handshake mode is supported by the following products. m m m m pd78f4216a, 78f4216ay: other than i, k, e standard m m m m pd78f4218a, 78f4218ay: other than i standard remark the fifth alphabetic character from the left in the lot number indicates the standard of the product. after executing the program command, execute the verify command to confirm the normal completion of the write operation. handshake mode is the csi write mode that uses p24.
data sheet u14125ej1v0ds00 46 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay flash memory programming characteristics (v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v, v pp = 9.7 to 10.3 v) (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit v pp setup time t psron v pp high voltage 1.0 m s v pp - setup time to v dd - t drpsr v pp high voltage 10 m s reset - set up time to v pp - t psrrf v pp high voltage 1.0 m s v pp count start time from reset - t rfcf 1.0 m s count execution time t count 1.0 ms v pp counter high-level width t ch 8.0 m s v pp counter low-level width t cl 8.0 m s v pp counter noise elimination width t nfw 40 ns flash memory write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph v ppl v pp v pp t rfcf t psron t psrrf t drpsr t ch t cl t count
data sheet u14125ej1v0ds00 47 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 8. package drawings remark the external dimensions and material of the es version are the same as those of the mass-produced version. 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 - 0.04 m 0.17 + 0.03 - 0.07 r3 + 7 - 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
data sheet u14125ej1v0ds00 48 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay remark the external dimensions and material of the es version are the same as those of the mass-produced version. 80 81 50 100 1 31 30 51 100-pin plastic qfp (14x20) hi j detail of lead end m q r k m l p s s n g f note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 23.6 0.4 20.0 0.2 0.30 0.10 0.6 h 17.6 0.4 i c 14.0 0.2 0.15 j 0.65 (t.p.) k 1.8 0.2 l 0.8 0.2 f 0.8 p100gf-65-3ba1-4 n p q 0.10 2.7 0.1 0.1 0.1 r5 5 s 3.0 max. m 0.15 + 0.10 - 0.05 c d a b s
data sheet u14125ej1v0ds00 49 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay 9. recommended soldering conditions the m pd78f4218ay should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 9-1. surface mounting type soldering conditions (1) m m m m pd78f4216agc-8eu:100-pin plastic lqfp (fine pitch) (14 14) m m m m pd78f4218agc-8eu:100-pin plastic lqfp (fine pitch) (14 14) m m m m pd78f4216aygc-8eu:100-pin plastic lqfp (fine pitch) (14 14) m m m m pd78f4218aygc-8eu: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ir35-107-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vp15-107-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) - note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). (2) m m m m pd78f4216agf-3ba:100-pin plastic qfp (14 20) m m m m pd78f4218agf-3ba:100-pin plastic qfp (14 20) m m m m pd78f4216aygf-3ba:100-pin plastic qfp (14 20) m m m m pd78f4218aygf-3ba: 100-pin plastic qfp (14 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less ir35-00-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: two times or less vp15-00-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) ws60-00-1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) - caution do not use different soldering methods together (except for partial heating).
data sheet u14125ej1v0ds00 50 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay appendix a. development tools the following development tools are available for system development using the m pd78f4218ay. also refer to (5) cautions on using development tools . (1) language processing software ra78k4 assembler package common to 78k/iv series cc78k4 c compiler package common to 78k/iv series df784218 device file common to m pd784216a, 784216ay, 784218a, 784218ay subseries cc78k4-l c compiler library source file common to 78k/iv series (2) flash memory writing tools flashpro ii (part number: fl-pr2), flashpro iii (part number: fl-pr3, pg-fp3) dedicated flash programmer for microcontroller incorporating flash memory fa-100gf adapter for writing 100-pin plastic qfp (gf-3ba type) flash memory. connection must be performed in accordance with the target product. fa-100gc adapter for writing 100-pin plastic lqfp (gc-8eu type) flash memory. connection must be performed in accordance with the target product. (3) debugging tools when ie-78k4-ns in-circuit emulator is used ie-78k4-ns in-circuit emulator common to 78k/iv series ie-70000-mc-ps-b power supply unit for ie-78k4-ns ie-70000-98-if-c interface adapter required when pc-9800 series pc (except notebook type) is used as host machine (c bus supported) ie-70000-cd-if-a pc card and cable when pc-9800 series notebook pc is used as host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter required when using ibm pc/at tm compatibles as host machine (isa bus supported) ie-70000-pci-if interface adapter required when using pc that incorporates pci bus as host machine ie-784225-ns-em1 emulation board to emulate m pd784216a, 784216ay, 784218a, 784218ay subseries np-100gf emulation probe for 100-pin plastic qfp (gf-3ba type) np-100gc emulation probe for 100-pin plastic lqfp (gc-8eu type) ev-9200gf-100 socket to be mounted on a target system board made for 100-pin plastic qfp (gf-3ba type) tgc-100sdw conversion adapter to connect the np-100gc and a target system board on which a 100-pin plastic lqfp (gc-8eu type) can be mounted id78k4-ns integrated debugger for ie-78k4-ns sm78k4 system simulator common to 78k/iv series df784218 device file common to m pd784216a, 784216ay, 784218a, 784218ay subseries
data sheet u14125ej1v0ds00 51 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay when ie-784000-r in-circuit emulator is used ie-784000-r in-circuit emulator common to 78k/iv series ie-70000-98-if-c interface adapter required when pc-9800 series pc (except notebook type) is used as host machine (c bus supported) ie-70000-pc-if-c interface adapter required when using ibm pc/at and compatibles as host machine (isa bus supported) ie-70000-pci-if interface adapter required when using pc that incorporates pci bus as host machine ie-78000-r-sv3 interface adapter and cable required when ews is used as host machine ie-784225-ns-em1 emulation board to emulate m pd784216a, 784216ay, 784218a, 784218ay subseries ie-784000-r-em emulation board common to 78k/iv series ie-78k4-r-ex3 emulation probe conversion board required when using ie-784225-ns-em1 on ie-784000-r. ep-784218gf-r emulation probe for 100-pin plastic qfp (gf-3ba type) ep-78064gc-r emulation probe for 100-pin plastic lqfp (gc-8eu type) ev-9200gf-100 socket to be mounted on a target system board made for 100-pin plastic qfp (gf-3ba type) tgc-100sdw conversion adapter to connect the ep-78064gc-r and a target system board on which a 100-pin plastic lqfp (gc-8eu type) can be mounted id78k4 integrated debugger for ie-784000-r sm78k4 system simulator common to 78k/iv series df784218 device file common to m pd784216a, 784216ay, 784218a, 784218ay subseries (4) real-time os rx78k/iv real-time os for 78k/iv series mx78k4 os for 78k/iv series
data sheet u14125ej1v0ds00 52 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay (5) cautions on using development tools the id78k4-ns, id78k4, and sm78k4 are used in combination with the df784218. the cc78k4 and rx78k/iv are used in combination with the ra78k4 and df784218. the fl-pr2, fl-pr3, fa-100gf, fa-100gc, np-100gf, and np-100gc are products made by naito densei machida mfg. co., ltd. (tel: +81-44-822-3813). the tgc-100sdw is a product made by tokyo eletech corporation. for further information, contact daimaru kogyo, ltd. tokyo electronic division (tel: +81-3-3820-7112) osaka electronic division (tel: +81-6-6244-6672) for third party development tools, see the single-chip microcontroller development tool selection guide (u11069e). the host machine and os suitable for each software are as follows: pc ews host machine [os] software pc-9800 series [windows] ibm pc/at and compatibles [japanese/english windows] hp9000 series 700 tm [hp-ux tm ] sparcstation tm [sunos tm , solaris tm ] news tm (risc) [news-os tm ] ra78k4 ? note ? cc78k4 ? note ? id78k4-ns ?- id78k4 ?? sm78k4 ?- rx78k/iv ? note ? mx78k4 ? note ? note dos-based software
data sheet u14125ej1v0ds00 53 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay appendix b. related documents documents related to devices document name document no. m pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay data sheet u14121e m pd78f4216a, 78f4216ay, 78f4218a, 78f4218ay data sheet this document m pd784216a, 784216ay subseries users manual hardware u13570e m pd784218a, 784218ay subseries users manual hardware u12970e 78k/iv series users manual instructions u10905e 78k/iv series instruction table - 78k/iv series instruction set - 78k/iv series application note software basics - documents related to development tools (user?s manuals) document name document no. language u11162e ra78k4 assembler package operation u11334e ra78k structured assembler preprocessor u11743e language u11571e cc78k4 c compiler operation u11572e ie-78k4-ns u13356e ie-784000-r u12903e ie-784218-r-em1 u12155e ie-784225-ns-em1 u13742e ep-78064 eeu-1469 sm78k4 system simulator windows based reference u10093e sm78k series system simulator external part user open interface specifications u10092e id78k4-ns integrated debugger pc based reference u12796e id78k4 integrated debugger windows based reference u10440e id78k4 integrated debugger hp-ux, sunos, news-os based reference u11960e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
data sheet u14125ej1v0ds00 54 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay documents related to embedded software (user?s manuals) document name document no. fundamental u10603e installation u10604e 78k/iv series real-time os debugger - 78k/iv series os mx78k4 fundamental - other documents document name document no. semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e guide to microcomputer-related products by third party - caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
data sheet u14125ej1v0ds00 55 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay [memo]
data sheet u14125ej1v0ds00 56 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay [memo]
data sheet u14125ej1v0ds00 57 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay [memo]
data sheet u14125ej1v0ds00 58 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. iebus is a trademark of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation.
data sheet u14125ej1v0ds00 59 m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
m m m m pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. m8e 00. 4 the information in this document is current as of august, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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